During a front end-of-the-line (FEOL) semiconductor fabrication process, a plurality of semiconductor devices (e.g., transistors, resistors, and the like) is generally formed on a semiconductor substrate. During a back end-of-the-line (BEOL) semiconductor fabrication process, the semiconductor devices are connected by a network of electrically-conductive lines, vias, and interconnect structures. The network of electrically-conductive lines, vias, and interconnect structures selectively connect the semiconductor devices to each other and to various other devices such as, but not limited to, a power source, clocks, signals, addresses, and input and output sources, and also connect the semiconductor devices to subsequently-formed semiconductor devices. In this manner, a plurality of integrated circuits (ICs) is formed on the semiconductor substrate with electrical connection enabled through the network of electrically-conductive lines, vias, and interconnect structures.
To enable efficient interconnection of the semiconductor devices to each other and to a power source, electrically-conductive vias are integrally formed within the semiconductor substrate and extend across various levels of integrated circuits to provide power to the different levels. Such electrically-conductive vias are known in the art as through-semiconductor vias. The through-semiconductor vias are formed during the BEOL semiconductor fabrication process by selectively etching a recess through any dielectric layers that overlie the semiconductor substrate and at least partially into the semiconductor substrate, followed by depositing metal such as copper in the recess and chemical-mechanical planarization (CMP) to remove excess metal from outside of the recess. Subsequent layers are then formed over the dielectric layers and the through-semiconductor via, including a metal layer that selectively connects the through-semiconductor vias to a power source and to the semiconductor devices.
Void formation is a common problem associated with forming subsequent layers over the through-semiconductor via. Without being bound to any particular theory, it is believed that void formation is attributable to migration of metal ions from the through-semiconductor vias into the interface between the through-semiconductor vias and the metal layer or dielectric layers that overlie the through-semiconductor vias. It is believed that the migration of the metal ions causes stress-induced warping in the subsequent layers, thereby creating voids between the through-semiconductor vias and the metal layer that overlies the through-semiconductor vias. As a result of void formation, connections between the through-semiconductor vias and the subsequent layers may be compromised at various locations, resulting in loss of electrical communication between the through-semiconductor vias and the subsequent metal layer that overlies the through-semiconductor vias.
In addition to void formation between through-semiconductor vias and subsequent layers being a common problem, robust connection between subsequently-formed metal layers and the through-semiconductor vias presents difficulties, especially as feature dimensions continually shrink. Ineffective etching and fragile pattern features correlate to higher rates of defect formation in the integrated circuits. In particular, ineffective etching may result as pattern features (in particular, gaps or recesses in the pattern) become so small that intended sites of recess formation are missed. Further, fragile pattern features may be broken during various processing techniques such as CMP or etching.
Accordingly, it is desirable to provide integrated circuits and methods of forming integrated circuits that minimize or alleviate void formation between through-semiconductor vias and subsequent layers that overlie the through-semiconductor vias. It is also desirable to provide methods of forming integrated circuits that minimize the incidence of defect formation in connection with ineffective etching and fragile pattern features. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.